There has been an increased need for high speed of operation made possible by the increased integration density of semiconductor memory devices without the increased noise generally accompanying such high speed operations.
One method proposed to increase the operation speed of the device is an ATD (Address Transition Detection) technology, wherein clocks are generated internally by detecting changes of address or control signals rather than being supplied from the outside. More specifically, since a 16 read/write operation is performed after precharging of data lines with a predetermined voltage for the operation of read/write using internal pulse, increased speed may be achieved.
However, when precharging data lines, it takes a long period of time to charge up to the power supply voltage (Vcc) from the ground voltage (Vss), and noise is generated inside the chip during precharging of the data lines having a large voltage swing. The noise thus gernerated has a negative effect on the operation of the device.
To solve this problem, a method for reducing the swing of the signal of the data lines has been proposed as described on page 1214 of the IEEE JOURNAL OF SOLIDSTATE CIRCUITS VOL. 24, NO. 5, OCTOBER 1989. This method is effective in the case of performing a continuous read operation, but still is not satisfactory in connection with the operation speed and noise reduction when the read operation is carried out after a write operation. More specifically, since a write driver allots the respective data lines with a ground voltage (Vss) and a power supply voltage (Vcc), or alternatively with a ground voltage and a power supply voltage minus a threshold voltage of a NMOS transistor (Vcc-Vtn) during the performance of a write operation, it takes a long period of time to precharge up to the power supply voltage (Vcc) or the power supply voltage minus the threshold voltage of NMOS transistor (Vcc - Vtn) required when a data line is precharged to perform a read operation after a write operation. Such a long period of time gives rise to noise.
To explain this kind of conventional method in greater detail, reference will be particularly made to FIG. 1 wherein another conventional write driver of a SRAM device is illustrated.
The write driver is connected with a pair of data input terminals DL and DLB which are respectively coupled to a pair of internal data lines BL and BLB, which are in turn connected to a memory cell MC through input/output gates IOG. The write driver includes a noninverted data driver 1 which noninverts the data input signal DIN applied to the data input terminals from outside in response to the write enable signal WE and includes an inverted data driver 2 which inverts the data input signal DIN in response to the write enable signal WE.
The noninverted data driver 1 includes a NAND gate NAND1 generating a signal A by inverting the data input signal DIN in response to the write enable signal WE; a NAND gate NAND2 and inverter INV2 generating a signal B by noninverting the inverted data input signal DINB which has been generated by inverting the data input signal DIN through an inverter INV1; a pull-up transistor MN1, a gate of which receives the signal A and a drain of which is connected to the noninverted data line DL; and a pull-down transistor MN2, a gate of which receives the signal B and a drain of which is connected to the noninverted data line DL.
The inverted data driver 2 includes a NAND gate NAND3 generating a signal C by inverting the inverted data input signal DINB in response to the write enable signal WE; a NAND gate NAND4 and inverter INV3 generating a signal D by noninverting the data input signal DIN in response to the write enable signal WE; a pull-up transistor MN3, a gate of which receives the signal C and a drain of which is connected to the inverted data line DLB; and a pull-down transistor MN4, a gate of which receives the signal D and a drain of which is connected to the inverted data line DLB.
The operation of the conventional write driver illustrated in FIG. 1 will be explained with reference to FIG. 2. In writing data into a memory cell, when a write enable signal WE becomes level "H" (i.e., high) and a data input signal DIN falling down to "L" (i.e., low) from "H" is input, an inverted data input signal DINB rising up to "H" from "L" is generated through the inverter INV1. The noninverted data input signal DIN together with write enable signal WE generate inverted signal A through NAND gate NAND1 and the inverted data input signal DINB together with write enable signal WE generate noninverted signal B though NAND gate NAND2 and inverter INV2. Here, the signals A and B rise up to "H" from "L". The signal A turns the pull-up transistor MN1 OFF and the signal B turns the pull-down transistor MN2 ON, causing the noninverted data line DL to be in a state of ground voltage Vss by pulling down. The inverted data input signal DINB together with write enable signal WE generate inverted signal C through a NAND gate NAND3, and noninverted data input signal DIN together with write enable signal WE generate noninverted signal D through NAND gate NAND4 and inverter INV3. Here, the signals C and D fall down to "L" from "H". The signal C turns the pull-up transistor MN3 ON and the signal D turns the pull-down transistor MN4 OFF, causing the inverted data line DLB to be in a state of power supply voltage Vcc by pulling up.
When a write enable signal WE falls down to "L" to perform a read operation after the write operation, signal A remains at "H", signal B changes to "L" from "H", signal C changes to "H" from "L" and signal D remains at "L". Accordingly, transistors MN1, MN2, MN3 and MN4 are all turned OFF, and a write driver and a pair of data lines are electrically separated.
When precharging a pair of data lines to read out data in the memory cell, a pair of data lines are allotted with the power supply voltage Vcc and the ground voltage Vss, and thus a long period of time is required to precharge the data. As result, noise is generated for precharging the data lines having a large swing, leading to a negative effect on device operation.